Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability. The capabilities of and specifications for XILINX FPGAs are set forth in "The Programmable Logic Data Book," published in 1998 by XILINX, Inc., the contents of which is incorporated herein by reference.
Linear feedback shift registers (LFSRs) are commonly used in applications for generating pseudo-random noise sequences. The pseudo-random noise sequences are commonly referred to as "PN codes" or "PN sequences." Such noise sequences have a diverse range of uses, several of which are found in spread spectrum communications systems. The growing popularity of wireless communications systems has lead to the adoption of spread spectrum technology in an attempt to maximize utilization of the available radio signal bandwidth.
LFSR's are at the heart of every spread spectrum system as they are used to uniquely code each subscriber signal and spread the transmission signal across a wide range of frequencies. An LFSR generally comprises a shift register of one bit memory elements and an XOR feedback path. An LFSR can be achieved in both FPGA and ASIC technologies. However, it is always desirable to achieve a given functionality using the minimum number of resources since silicon resources of both ASICs and FPGAs are finite.
An example spread spectrum system, the Universal Mobile Telecommunication System (UMTS), requires a number of LFSRs that must be periodically set to a predefined state at a known time interval. The UTMS specification is controlled and maintained by the European Telecommunications Standards Institute (ETSI). This specification implies an LFSR structure that requires parallel access to all stages in the shift register such that the shift register's contents can be modified in one cycle of the LFSR clock rate. Implementing parallel access to the shift register stages requires additional logic resources, which is contrary to the objective of using as few resources as possible.
An apparatus that satisfies the aforementioned requirements, as well as other related requirements, is therefore desirable.